The manufacturing of a gate is a key step for a process for forming a semiconductor device, since the gate conventionally has a minimal physical dimension in the process of manufacturing a semiconductor device, i.e. the width of the gate conventionally is a critical dimension of the semiconductor device.
In the prior art, a method for forming a gate conventionally includes the following steps: forming a dielectric layer 20 on a semiconductor substrate 10, as shown in FIG. 1a; forming a polysilicon layer 30 on the dielectric layer 20, as shown in FIG. 1b; forming an etched resist layer 40 on the polysilicon layer 30, as shown in FIG. 1c; etching the polysilicon layer 30 by using the etched resist layer 40 as mask to form a gate 32.
As the critical dimension of the device decreases gradually, how to precisely controlling the width of a gate has become a primary problem interested by the skilled in the art. Many attempts has been tried to resolve this problem, for example, the Chinese patent publication No. CN 1855372A (disclosed on Nov. 1, 2006) discloses a method for forming a gate, in which a precise controlling for a width of the gate is achieved by avoiding horns generated on a top surface of the gate.
However, it is found in practice that a roughness 34 formed on the sidewalls of a gate also can affect the precise controlling for a width of the gate negatively in addition to the horns on the top surface, as shown in FIG. 1e. Conventionally, the roughness 34 is regarded to be formed due to a non-uniform etching during the process for forming a gate. The problem of improving the etching uniformity of sidewalls of a gate has attracted more attentions in the art.
Furthermore, shallow trench isolation (STI) process is a key process for isolating between active regions formed on a semiconductor substrate as the decrease in critical dimension of a device. The profile character of the shallow trench such as smoothness of the sidewalls and bottom surface of the shallow trench can facilitate to improve a precise controlling for the width and depth of the shallow trench isolation region, and in turn, a precise controlling for the width and depth of the shallow trench isolation region can facilitate to improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region.
In the art, a method for forming a shallow trench isolation region includes the following steps: forming an etched passivation layer 60 on a silicon substrate 50, as shown in FIG. 2a; etching a portion of the silicon substrate 50 by using the etched passivation layer 60 as a mask to form a shallow trench 52, as shown in FIG. 2b; and filling the shallow trench to form a shallow trench isolation region. A device active region has been defined in the silicon substrate.
However, it is found in practice that a roughness 54 is easily formed on the sidewalls of the shallow trench and it can affect the precise controlling for a width and depth of the shallow trench negatively, as shown in FIG. 2c. The roughness 54 is conventionally regarded to be formed due to a non-uniform etching during the process for forming the shallow trench. How to improve the etching uniformity of sidewalls and bottom surface of a shallow trench has attracted more attentions in the art.